The present invention generally relates to characterization for magnetoresistive random access memory (MRAM) devices, and more specifically, to the characterization of the performance of magnetic tunnel junction (MTJ) elements loaded in ring oscillators.
Magnetic random access memory (MRAM) devices include magnetic memory elements. The memory elements in MRAM devices include magnetic tunnel junction (MTJ) devices that can store data.
The magnetic device combined with microelectronics in MRAM allows for the design, manufacture and use of non-volatile memory devices. These devices can also be high speed operative devices. MRAM devices can be advantageous relative to other memory technologies such as dynamic random access memory (DRAM), static random access memory (SRAM) and Flash for several reasons. For example, MRAM devices can be non-volatile and consequently retain data even when completely turned off, thereby allowing system power savings. MRAM devices can also be cost effective due to the cell size of such devices. In some instances, MRAM also uses less energy for write characteristics and can possess a faster write cycle relative to some other memory technologies. MRAM devices can further provide the advantage of having unlimited endurance given that the devices do not typically deteriorate. MRAM devices can further be easily integrated with complementary metal oxide semiconductor (CMOS) technologies.
A technique long used to characterize performance of circuits on semiconductor chips is to place a number of the circuits in a ring oscillator (RO). Ring oscillators (ROs) typically include a series of devices or stages connected together to form a ring with a feedback path provided from the output of the last of the series of devices to an input of the first device in the series of devices. The devices may include logic gates, inverters, differential buffers, or differential amplifiers, for example. An inverting path with sufficient gain will oscillate when connected in a ring, while a non-inverting path will simply lock on a particular starting logic level. The ring oscillator is essentially a series of stages, each stage having an intrinsic delay from input to output. The frequency of the ring oscillator output is a function of the total delay time of the series of stages. Such ring oscillators have been common in ASCIs and processors to determine the speed characteristics of a particular chip.
Devices of similar design track well across a semiconductor chip. That is, a ring oscillator built out of inverters that are designed with high speed logic performs “fast,” all logic circuits on a particular chip utilizing similar high-speed logic will also perform “fast.” Some variation may be expected and the variation can be quantified in any given process. Placement of several ring oscillators at different areas of a chip design allows the designer to account for “cross chip” variations in performance. In very localized regions of a chip, parameters such as channel lengths track extremely well from one FET to another. Tracking of parameters between FETs at widely separated areas on a chip do not track as well as FETs that are very close. However, even FETs that are widely separated on a chip track better than chips processed on different wafers produced on different process lots, or even the same process lot.
Knowing the speed characteristics of a particular chip is valuable in order that the chip can be categorized as, for example, “fast,” “nominal,” or “slow”. Fast products are often more valuable than nominal or slow products. Such speed differentiation is sometimes known as “speed sorting” or “bucketing.”
Magnetic tunnel junction (MTJ) elements used in magnetoresistive random access memory (MRAM) devices include a first magnetic layer, a second magnetic layer and a non-magnetic layer positioned between the first and second magnetic layers. The first and second magnetic layers can be ferromagnetic layers while the non-magnetic layer can be an insulator layer such that current can tunnel through the non-magnetic layer between the first and second magnetic layers. Such MTJ structures are known to those skilled in the art. As also known to those skilled in the art, the structure and number of layers in a MTJ element that is part of a chip or memory device can include additional layers and/or the layers of the MTJ element and the chip can be formed from a variety of materials. Various manufacturing processes can also be used to make a MTJ element. The MTJ element will have a unique tunneling path through the non-magnetic layer and between the first and second magnetic layers. Because of the nature and structure of magnetic tunnel junction (MTJ) elements, the current that tunnels through such devices and its relationship to the switching characteristics is unique to each MTJ element even when such elements are manufactured in the same facility.
The increasing use of MRAM devices makes it increasingly important to be able to understand and properly characterize the switching characteristics of MTJ elements in MRAM devices at fast time scales. More specifically, there is a need to be able to efficiently characterize the performance of MTJ elements in real product like environments. Currently, such characterization is done by applying pulses from external pulse sources in a functional test environment. Besides involving complex logistics and expensive test equipment, this potentially introduces unwanted parasitics that can skew the results.
More specifically, current bit error rate testing methodology utilizes a functional tester with externally applied timing pulses. This involves complex logistics using expensive automatic test equipment (ATE) and can potentially, introduce parasitics that alter the results.